In classical VCO structures, low-frequency phase modulation (PM) noise, or long-term jitter, is significant and cumulative. Phase-locked loop (PLL) circuits using this kind of VCO are able to correct this PM noise or jitter only up to a modulation frequency equal to that of the PLL band width. At higher modulation frequencies, the PLL circuit stops regulating and so the PM noise is equal to or slightly higher than the intrinsic PM noise of the VCO. Reducing high frequency PM noise, short-term jitter, requires either a very large PLL bandwidth or a low noise VCO. Enlarging the PLL bandwith is limited by the fact that the bandwidth cannot exceed about 1/20th of the reference frequency, due to quantization noise. Hence, low noise VCO circuits are sought.
Phase realignment in a VCO circuit allows synchronizing its phase to that of a reference clock signal. In particular, the VCO clock edge may be resynchronized to each reference clock edge. This resynchronization has been realized by inserting realignment inverters having specific phase delays into the VCO ring. See, for example, the published international (PCT) patent application WO 03/063337A1 of Sheng et al. A realignment signal is obtained by combining the VCO circuit's clock output with a reference clock. This realignment signal is applied to one of the realignment inverters to force a transition at the reference clock edge. PLL circuits that use a phase-realigned VCO have reduced PM noise or jitter to significantly higher frequencies than comparable simple PLL circuits.
However, this technique also requires sophisticated digital gating and timing skewing between the VCO clock output, reference clock and realignment signal in order to apply the phase realignment at the optimum instant. The phase realignment factor, which is defined as the induced realignment phase shift divided by the difference between the VCO and reference phases just prior to the realignment instant, is minimally dependent on device performance spread and mismatch. The addition of realignment inverters adds phase delay to the VCO ring and thus decreases the VCO circuit's maximum operating frequency. The device parameters in any VCO circuit embodiment are specific to the design operating frequency, and hence this particular phase realignment technique is not applicable where a VCO circuit with a wide frequency range is desired.
In U.S. Pat. No. 5,495,205, Parker et al. describe a digital controlled oscillator where the individual stages include coarse and fine frequency tuning based on a capacitor load adjustment for each inverter in the oscillator ring. Varying the load capacitors of the ring inverters adjusts the propagation delay through the stages. Frequency tuning of the oscillator is based on a lag/lead flag generated by a phase detector. Additionally, phase realignment may be applied to one stage, based on a RESET signal. The single-stage phase realignment factor is strictly equal to one and fully resets the phase of the oscillator. An advantage of this construction is that it achieves a relatively large bandwidth for a VCO at moderate operating frequencies. But, the system is too slow for operations at high frequencies.